1. Field of Invention
The invention relates to an electrostatic discharge (ESD) protection circuit and an integrated circuit.
2. Related Art
Electrostatic discharge (ESD) issue is a key factor to cause the damage to the most electronic elements or systems. ESD is usually formed by the human cause and also difficult to be avoided. For example, the static electricity will be accumulated in the human body, appliances, storage devices and even electronic elements in the manufacturing, production, assembly, testing, storage and conveying process of the electronic element or system. The workers may unknowingly make these objects contact each other and an ESD path is thus formed. Therefore, the electronic element or system will be damaged by the ESD. This kind of damage may result in the permanent harm for the semiconductor device or computer system and the electronic product or system thus malfunctions. Therefore, in order to assure the efficiency of the electronic circuit, especially of the IC chip, the ESD protection circuit is indispensible.
According to the principle of the transistor, when the size of the transistor is smaller, a higher operation frequency can be obtained. Hence, since the device manufacturing has reached nanoscale, the operation frequency of the transistor is favorably increased due to the rapid development of the scaled down technology. However, for the scaled-down transistor, ESD is the main factor influencing the reliability thereof. Therefore, a proper ESD protection circuit needs to be designed to prevent the circuit device from being damaged by the ESD. Especially in the application of the high-frequency integrated circuit, with the operation frequency from several GHz to dozens of GHz and even to hundreds of GHz for example, the ESD protection circuit not only needs a sufficiently high ESD immunity but also a very low parasitic capacitance, or the loading caused by the parasitic capacitance will result in the performance reduction of the circuit.